1. Field of the Invention
This invention relates generally to digital signal processing systems implementing decision feedback equalizers, and particularly, to a low-cost and high-speed multiplier accumulator cell design for decision feedback equalizer implementations.
2. Discussion of the Prior Art
Decision Feedback Equalization is a technique used to eliminate all inter-symbol interference (ISI) caused by the transmission channel in digital communication systems. FIG. 1 is a schematic illustration of a typical Decision Feedback Equalizer (DFE) system 10. As shown in FIG. 1, the typical DFE includes a feed forward path including a first finite impulse response (FIR) filter 12, a feedback path 13 including a second FIR filter 14, a decision device 15, and, an error calculator 18. The input symbol xn represents the symbol inputs which are input to the first finite impulse response (FIR) filter 12. It is understood that first and second FIR filters 12, 14 are linear transversal filters each representing an adaptive transfer function ƒ(n), g(n), respectively according to respective sets of adaptable coefficients fn, gn. In operation, the output of the first FIR filter 12 is summed with the output of the feedback FIR filter 14 section to provide a desired DFE output represented as signal νn 20. The equalizer output νn may be described by the following equation 1):             1      )        ⁢                  ⁢          v      n        =                    ∑                  k          =          0                                      N            1                    -          1                    ⁢                        f          k                ⁢                  x                      n            -            k                                +                  ∑                  k          =          0                                      N            2                    -          1                    ⁢                        g          k                ⁢                  y                      n            -            k                              
Where N1 is the length of the forward filter f, N2 is the length of the feedback filter g, k is the index, and yn is the intermediate signal output of the decision device 15. In operation, the coefficients of each of the forward FIR filter 12 and feedback FIR filter 14 recursively adapt according to an output error signal en 16 of the feedback path until some convergence factor or error metric, e.g., mean square error, is satisfied. As shown in FIG. 1, the output error signal en 16 of the feedback path represents the difference between an input reference signal 21, i.e. a desired output signal, and the intermediate output signal yn 21 which is an output of decision block 15. As known to skilled artisans and described in the book “Digital Communications” by John G. Proakis, McGraw-Hill, 1995, 3rd ed., Ch. 11–2, pages 650 et seq., (ISBN 0-07-05-51726-6), the whole contents and disclosure of which is incorporated by reference as if fully set forth herein, the equalizer coefficients gn are adjusted recursively in the adaptive mode of the DFE.
FIG. 2 is a schematic diagram illustrating a typical implementation of a hardware unit 20 of the second (feedback path) FIR filter 14 for carrying out a second term summation in the convolution operation set forth in equation 1). In order to generate the coefficients, as shown in FIG. 2, the gn and yn input symbols are multiplied by a multiplier unit 25 and current the result is stored and added by adder unit 26 to the previous result value stored in accumulator register 29 to carry out the convolution operation.
The Decision Feedback Equalizers (DFE) implemented in North America Terrestrial Digital TV reception function according to the Advanced Television Systems Committee ATSC (8-VSB) DTV standard. According to this ATSC 8-VSB standard (as described at http://www.atsc.org/), eight amplitude levels are available for supporting up to 19.28 Mbps of data in a single 6 MHZ channel. Further, in accordance with the standard, the input yn of the feedback FIR filter is permitted to have discrete values only. For example, for the ATSC (8-VSB) DTV standard, the input yn of the feedback FIR filter can only have the values {−7, −5, −3, −1, 1, 3, 5, 7}. Referring back to FIG. 1, it is the decision device 15 that converts its input to one of these eight values by selecting one of those values that is closest to its input νn. In practice, these eight values are represented as a 4-bit, two's complement number, yn, so that they are suitable for a two's complement based arithmetic that is often used in digital computations. Assuming the feedback filter coefficients gn are N-bit, such two's complement representation require a 4-bit by N-bit multiplier device represented as multiplier accumulator device 25 (FIG. 2). Such multipliers are usually used in combination with an accumulator as shown in FIG. 2.
While the input data has only eight levels, the conventional implementation required the use of a 4×N-bit multiplier. This means that there is significant redundancy in the multiplier resulting in increased silicon cost. In addition, such a configuration is unnecessarily slow as the propagation time is dominated by the multiplier and the final adder.
It would thus be highly desirable to provide a multiplier/accumulator unit for a DFE that implements a feedback filter equalizer for performing convolution operations using reduced hardware, i.e., silicon area.
It would thus be highly desirable to provide a multiplier/accumulator unit for a DFE that performs convolution operations at great speeds without redundancy.